Overview

The L8051XC1 is a synthesizable soft HDL core of a 8-bit MCS®51-compatible microcontroller. It executes the MCS®51 instruction set and specially designed to match the timing and peripherals of legacy 8051 MCU based systems. 

The core can be configured to execute an instruction every 12, 6, or 4 clock cycles. Architectural extensions are user-selectable, including multiple data-pointers, a multiply-division unit, and a power management unit. Furthermore, the 8051 CPU can be coupled with a wide range of peripherals matching the behavior and timing of peripherals found in legacy architectures from Intel, Phillips/NXP, Siemens/Infineon, Maxim/Dallas, Texas instruments and others. Several pre-configured versions are offered; custom variations are also available. 

The L8051XC1 runs legacy code, but new software development is facilitated through one on-chip debugging option, and debug pods that cooperate with IAR Embedded Workbench & Keil uVision™ IDEs. Which can operate seamless within IDESs including those from Keil and IAR. 

The L8051XC1 builds on our engineering team’s rich experience on the proven 8051 family of processor cores, which have been successfully implemented in hundreds of different customer products since 1997. It is royalty-free and can be purchased with a custom configuration by selecting a set of options.